GitHub

sd_controller_fifo_wb.v

assign sd_adr_o = fifo_acces_token ? sd_adr_o_cmd : sd_adr_o_dat; assign sd_dat_o = fifo_acces_token ? sd_dat_o_cmd : sd_dat_o_dat; assign sd_we_o = fifo_acces_token ...
IEEE

Design of Low Power UART Architecture with FIFO Buffering for High-Speed Applications

Abstract: UART-FIFO controller is also a good technique to make sure that serial communication in an embedded system and Internet of Things (IoT) is secure and reliable. The suggested architecture ...
Design-Reuse

SPI Master / Slave Controller w/FIFO (APB Bus)

The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS ...
GitHub

cust_afu_cdc_fifo.sv

input cust_afu_treg_req_t treg_req , //from EP input cust_afu_treg_ack_t treg_ack , //from CFG output cust_afu_treg_req_t treg_req_fifo , output cust_afu_treg_ack_t ...
IEEE

FSM-Based Traffic Light Controller with Emergency Override

Abstract: Urban traffic backups often lead to significant delays for emergency vehicles, such as ambulances, fire trucks, and police cars, which can have major consequences. According to a World ...